Jonathan Xue
UCLA Computer Engineering student
Projects
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Designed and verified an audio visualizer on an Altera
MAX10 FPGA using SystemVerilog.
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Implemented a radix-2 64-point DIT FFT to filter sound
into frequency bins from an analog microphone.
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Displayed the frequency bins using a double-buffered VGA
controller to prevent screen tearing.
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Designed and verified a RISC-V 32I (base integer
instructions) processor running on an Arty A7-100T FPGA
using Verilog.